The Center projects are organized into
the following themes: Design of Communications Systems, CAD Tools and Methodologies,
|Design of Communication Systems:|
Design of a Hermitian Decoder IC
(Blahut, Koetter, O'Sullivan, Shanbhag)
This project explores the design of a decoder for Hermitian codes, which are believed to be the next generation of error control codes. Hermitian codes are a subset of algebraic-geometric codes that enable the block size to be greater than that of the Reed Solomon codes for the same Galois field. A 1.2 million transistor IC in 0.35mm CMOS has been designed to demonstrate these ideas.
Low-Power Video Over Wireless Channels
(Jones, Ramchandran, Shanbhag)
This project seeks to develop energy-efficient techniques to transmit video over wireless channels. We employ Joint Source-Channel Coding (JSCC) and dynamic algorithm transforms (DAT) in order to jointly optimize algorithms and architectures. See the JSCC web site for more details.
Low-Power VLSI Algorithms and Architectures for DSL
This research seeks to develop low-power equalizer architectures for digital subscriber loop applications, which include receivers based upon a discrete multitone transmission (DMT) scheme for asymmetric digital subscriber loops (ADSL), carrierless amplitude and phase (CAP) modulation for very high-speed digital subscriber loops (VDSL), and asynchronous transfer mode (ATM) local area networks (LANs). System partitioning of functionality into programmable and dedicated processing units is being determined to achieve the lowest power. A key feature of our approach is the joint optimization of algorithmic performance and power dissipation via the application of algebraic, Hilbert, and dynamic algorithm transformations.
Dynamic Algorithm Transformations for Low-Power Communication System
The goal of this research is to develop configurable modules for signal
processing and communication systems. Parametrizable modules for commonly
employed blocks such as equalizer, Reed-Solomon coders and decoders, and
motion-estimators are being designed. These blocks have the property that
the power consumption is a function of the data and the environment. Thus,
power-aware reconfigurable signal-processing systems can be designed via
such blocks. The usefulness of the research is being demonstrated by employing
it in the design of a cable modem.
|Integrated Circuit Design:|
Low-Voltage Digital CMOS Circuits
State-of-the-art VLSI chips are being used in portable systems that require compactness, high speed, and long battery life. New innovative circuit design techniques are required for high speed with low power consumption. Power-minimum high-speed circuit design methods with charge recycling are being developed to drastically reduce the power consumption of low-voltage CMOS circuits. Several benchmark circuits such as adders and multipliers are used to demonstrate significant power savings and low leakage currents without resorting to power supply scaling, substrate biasing, or threshold voltage tuning.
Reliable High-Speed I/O Circuits
In deep submicron technology, the speed and ESD reliability of I/O circuits play a critical role note only in chip-to-chip interface, but also protection of internal circuits. The conflicting requirements between high speed and high reliability must be met through rigorous analysis and innovative design concepts. Various circuit and device techniques are being investigated for high-speed VLSI chip applications. Testers have been designed, fabricated, and characterized for proof-of-concept and practical applications in close collaboration with industry.
Noise-Tolerant DSP in the Deep Submicron Era
This research addresses the design of reliable and energy-efficient
DSP systems in deep submicron (DSM) SMOS technology in a unified manner
via the development of noise-tolerant algorithmic and circuit design techniques.
In particular, circuit design techniques that tolerate leakage, crosstalk,
ground bounce, and process variations are being developed. Algorithmic
approaches that exploit the statistical structure of multimedia signals
to combat DSM noise are also being studied. A design methodology is being
formulated that jointly applies circuit and algorithmic noise-tolerance
techniques to achieve an overall level of system reliability while minimizing
|CAD Tools and Methodologies:|
Timing Verification of VLSI Circuits Including Coupled Interconnect Effects
The aim of this research is to develop numerical methods and computer algorithms for estimating delay and coupling noise in digital VLSI circuits caused by interconnect parasitics and cross-coupling capacitance. With the increase in the operating frequency, interconnects are becoming the dominant factor in determining the performance of current and future designs. This task aims at assessing the impact of interconnects on the performance and signed integrity of the design. The results are used for design optimization.
Analysis and Design for Reliable Noise-Resistant VLSI Circuits
Our goal is to develop computer-aided design techniques for predicting the reliability of VLSI circuit designs to detect if and when the design does not meet reliability specifications and to recommend changes in the design to meet these specifications. In our work, we have derived statistical techniques as well as worst-case estimation methods that allow design for reliability to be done at a reasonable cost. The results give an estimate of the average and maximum power drawn by different parts of the design. Fast methods for estimating worst-case voltage drop in the power bus, worst-case current flows in the bus for electromigration estimation, and leakage current, are being developed. Design techniques for enhancing noise immunity are being pursued.
An Integrated Design Methodology for Low Power DSP and Communications Systems
The goal of this project is to develop an integrated computer-aided design (CAD) approach for the design of low-power hardware for digital signal processing (DSP) and communication applications. The approach incorporates high-level (algorithmic) and low-level (circuit) parameters and includes novel capabilities for design exploration and low-power constrained algorithm design procedures that employ an analytic relation between word-level and bit-level signal statistics. The synthesis effort will incorporate signal statistics, high-level hardware models, and algorithm transformations to generate low-power dedicated implementation of DSP algorithms.
Composite CAD for Microelectromechanical Systems (MEMS)
MEMS finds many unique applications in communication systems and sensory systems. Micromechanical systems can be integrated with microelectronic systems on a common substrate. For the development of such systems, new CAD models and simulation tools are essential. In this project, new models for mechanical switches, tunable capacitors, and other core components are being developed for their use in mixed-level, mixed-signal simulation. One of the highly challenging modeling tasks is to develop a systematic nonlinear model reduction technique, especially for micromechanical systems, and this challenging problem is being addressed.
Domino Logic Synthesis
CMOS domino logic has been widely used for high-speed VLSI circuits and systems. Due to the inherent non-converting nature of domino logic, duplicate logic had to be used with significant area penalty. In the project, we apply implication graph theoretic approach to minimize duplicated logic by maximizing the inverter-free logic portion. For inverter elimination, automatic test pattern generation techniques are adopted. Preliminary results show as much as 30% improvement of the CMOS technology power.
Tool-Independent, Circuit-Level Models of ESD Protection Devices
We use Verilog-A to develop simulator- and platform-independent models of ESD protection devices in both the on-state (high current) and off-state (normal operating conditions).
Temperature-Dependent Reliability Simulation and Placement
The temperature-dependent electromigration diagnosis tool, iTEM, which may also be used for temperature-dependent timing simulation will be enhanced. Its capability to analyze VLSI-scale circuits will be improved by addition of a gate-level simulator for power and current estimation. The interconnect thermal modeling has been extended to account for the heat sinking capability of dense interconnect meshes. A temperature-dependent automatic placement and routing tool is being developed for both standard cells and macromodules. Routing will be performed such that timing and reliability specifications are met.
Timing Simulation of High-Speed CMOS Logic Including RLCG Interconnects
The interconnects for high-speed circuits and systems need to be modeled accurately in order to examine the signal integrity and signal propagation delay times. In this project, we have developed new modeling and simulation techniques for time-efficient and accurate simulation of interconnect lines in conjunction with fast MOS timing simulator ILLIADS. In particular, the interface issues between Ricatti solver and the model reduction for transmission line analysis have been investigated for time-efficient and accurate timing simulation of very high-speed VLSI circuits wherein inductance effects become important. Main results have been implements in ILLIADS-I program.
SOI-Specific Physical Design Flow
We are developing design guidelines for fast and reliable SOI CMOS logic gates. We have also developed a bipolar leakage model for approximate simulators; this is needed to predict data upset in SOI circuits that use floating-body transistors.
Timing Verification for SOI Circuits
Silicon-on-insulator (SOI) logic circuits are becoming popular because of their low-power and low-noise advantages compared to standard CMOS. A major difficulty with the verification of circuits built of partially depleted floating-body SOI is that the threshold voltage (and hence the speed) of the SOI circuits is variable and depends on their operational history. We are developing techniques for verifying SOI circuits that take into account these gate delay variations.
Analysis of Substrate Noise Coupling in Mixed-Signal Circuits
Noise coupling through the common silicon substrate is a particular concern
for mixed-signal circuits. Noise coupling arises when current is injected into
the silicon substrate. Sources of current injection include (i) displacement current flow from n+ source/drain diffusions into the
p-substrate, and (ii) the substrate current which results from impact ionization
near the drain of a MOSFET and (iii) ground bounce on the substrate
taps. We are working have developed an accurate and computationally efficient tool for constructing an electrical model of the substrate, given the chip layout and substrate doping profile. The resulting electrical network will be simulated in SPICE along with the active devices for a complete description of the circuit behavior including the effects of substrate noise coupling.
Substrate Noise Coupling
We have developed a 3D layout extractor which constructs a map of the chip substrate for subsequent electromagnetic analysis using the boundary element method; it also extracts the active devices for later circuit simulation. We are developing a comprehensive electromagnetic analysis tool to provide a transfer impedance matrix model of the substrate. The transfer impedances will be connected to the active devices in order to simulate the behavior of the circuit including the effects of noise coupling through the substrate.
ESD Protection for 10 GHz RF I/Os
We are doing concurrent design of RF integrated circuits and ESD protection circuits so as to achieve RF designs which have both acceptable performance and acceptable ESD protection levels. Historically, ESD protection has been left off the inputs of RFICs because the parasitic shunt capacitance reduces gain. However, this practice reduces yield and, with the move to ESD-sensitive CMOS as the RF technology of choice, it is becoming an unacceptable practice.
Fundamental Bounds on VLSI Computation
The goal of this research is to develop an information-theoretic basis of VLSI computation so that fundamental achievable bounds on VLSI performance (such as power, area, throughput) can be determined. Furthermore, methods to achieve these bounds are also being investigated. The usefulness of the proposed theory is being demonstrated via numerical calculations of lower bounds on power dissipation for simple static CMOS circuits as well as pipelined and parallel processing architectures.
CMOS Power Converters for Active, Distributed Power Management
The project involves designing low power, low voltage dc-dc converters using standard CMOS processes. The passive components are to be fully integrated. The technology will enable the power conversion circuitry to be distributed throughout a larger CMOS circuit so that local voltage and power management for specific subcircuits can be controlled. The potential advantages are increased integration and lower power dissipation.
|Contact iCIMS at:|
The Illinois Center for Integrated Microsystems (iCIMS)
Coordinated Science Laboratory
University of Illinois at Urbana-Champaign
1308 West Main Street
ph:(217)244-0041; fax:(217)244-1946; email:firstname.lastname@example.org