Deming Chen's Publications


    Book Chapters


  1. D. Chen, Chapter 4.8: Design Automation for Microelectronics, Handbook of Automation, Springer Publishers, to appear.


    2. JOURNAL PAPERS


  2. L. Cheng, D. Chen, and D.F. Wong, "DDBDD: Delay-Driven BDD Synthesis for FPGAs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, to appear.

  3. L. Cheng, D. Chen, and D.F. Wong, "A Fast Simultaneous Input Vector Generation and Gate Replacement Algorithm for Leakage Power Reduction," ACM Transactions on Design Automation of Electronic Systems, Vol. 13, No. 2, Article 34, Apr. 2008.

  4. C. Dong, D. Chen, S. Haruehanroengra, and W. Wang, "3-D nFPGA: A Reconfigurable Architecture for 3-D CMOS/Nanomaterial Hybrid Digital Circuits," IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 54, Issue 11, pp. 2489-2501, November 2007.

  5. D. Chen, J. Cong, and P. Pan, "FPGA Design Automation: A Survey," Foundations and Trends in Electronic Design Automation, Vol. 1, No 3, pp.195-330, November 2006.

  6. D. Chen, J. Cong, and J. Xu, "Optimal Simultaneous Module and Multi-Voltage Assignment for Low-Power," ACM Transactions on Design Automation of Electronic Systems, vol. 11, Issue 2, pp. 362-386, April 2006.

  7. F. Li, Y. Lin, L. He, D. Chen, and J. Cong, "Power Modeling and Characteristics of Field Programmable Gate Arrays," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, Issue 11, pp. 1712-1724, November 2005. (One of the most-downloaded papers from TCAD ranked by CEDA)

  8. D. Chen, J. Cong, M. Ercegovac, and Z. Huang, "Performance-Driven Mapping for CPLD Architectures," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 22, no. 10, pp. 1424-1431, October 2003.


    9. CONFERENCE PAPERS


  9. A. Papakonstantinou, Y. Kifle, G. Lucas, and D. Chen, "MP3 decoding on FPGA: A case study for floating point acceleration," Proceedings of Reconfigurable Systems Summer Institute, Urbana, IL, 2008.

  10. A. Papakonstantinou, D. Chen, and W.M. Hwu, "Enhancing Application Performance with EPOS: an Explicitly Parallel Operations System," IEEE Symposium on Application Specific Processors, 2008.

  11. Q. Dinh, D. Chen, and D.F. Wong, "Efficient ASIP Design for Configurable Processors with Fine-Grained Resource Sharing," ACM/SIGDA International Symposium on FPGA, February 2008.

  12. S. Akram, S. Cromar, G. Lucas, A. Papakonstantinou, and D. Chen, "VEBoC: Variation and Error-Aware Design for Billions of Devices on a Chip," IEEE/ACM Asia and South Pacific Design Automation Conference, January 2008. (Invited)

  13. C. Dong, D. Chen, S. Haruehanroengra, and W. Wang, "Performance and Power Evaluation of a 3D CMOS/Nanomaterial Reconfigurable Architecture," IEEE/ACM International Conference on Computer-Aided Design, Nov. 2007.

  14. L. Cheng, D. Chen, D.F. Wong, M. Hutton, and J. Govig, "Timing Constraint-driven Technology Mapping for FPGAs Considering False Paths and Multi-Clock Domains," IEEE/ACM International Conference on Computer-Aided Design, Nov. 2007.

  15. Q. Dinh, Y. Bresler, and D. Chen, "Hardware Acceleration for Sparse Fourier Image Reconstruction," IEEE International Conference on ASIC, Oct. 2007. (Invited)

  16. L. Cheng, D. Chen, and D.F. Wong, "GlitchMap: An FPGA Technology Mapper for Low Power Considering Glitches," IEEE/ACM Design Automation Conference, Jun. 2007.

  17. L. Cheng, D. Chen, and D.F. Wong, "DDBDD: Delay-Driven BDD Synthesis for FPGAs," IEEE/ACM Design Automation Conference, Jun. 2007.

  18. D. Chen, J. Cong, Y. Fan and Z. Zhang, "High-Level Power Estimation and Low-Power Design Space Exploration for FPGAs," IEEE/ACM Asia and South Pacific Design Automation Conference, Jan. 2007.

  19. L. Cheng, L. Deng, D. Chen, and D.F. Wong, "A Fast Simultaneous Input Vector Generation and Gate Replacement Algorithm for Leakage Power Reduction," IEEE/ACM Design Automation Conference, July 2006.

  20. J. Lin, D. Chen, and J. Cong, "Optimal Simultaneous Mapping and Clustering for FPGA Delay Optimization," IEEE/ACM Design Automation Conference, July 2006.

  21. D. Chen, J. Cong, Y. Fan, and J. Xu, "Optimality Study of Resource Binding with Multi-Vdds," IEEE/ACM Design Automation Conference, July 2006.

  22. D. Chen, J. Cong, Y. Fan, G. Han, W. Jiang, and Z. Zhang, "xPilot: A Platform-Based Behavioral Synthesis System," Proceedings of SRC Techcon Conference, October 2005.

  23. D. Chen, J. Cong, and J. Xu, "Optimal Module and Voltage Assignment for Low-Power," IEEE/ACM Asia and South Pacific Design Automation Conference, Shanghai, China, pp. 850-855, January 2005.

  24. D. Chen and J. Cong, "DAOmap: A Depth-Optimal Area Optimization Mapping Algorithm for FPGA Designs," IEEE/ACM International Conference on Computer-Aided Design, San Jose, California, pp. 752-759, November 2004.

  25. D. Chen and J. Cong, "Delay Optimal Low-Power Circuit Clustering for FPGAs with Dual Supply Voltages," International Symposium on Low Power Electronics and Design, Newport Beach, California, pp. 70-73, August 2004.

  26. D. Chen, J. Cong, F. Li, and L. He, "Low-Power Technology Mapping for FPGA Architectures with Dual Supply Voltages," Proceedings of the ACM International Symposiumon Field-Programmable Gate Arrays, Monterey, California, pp. 109-117, February 2004.

  27. D. Chen and J. Cong, "Register Binding and Port Assignment for Multiplexer Optimization," Proceedings of the Asia and South Pacific Design Automation Conference, Yokohama, Japan, pp. 68-73, January 2004.

  28. D. Chen, J. Cong, and Y. Fan, "Low-Power High-Level Synthesis for FPGA Architectures," International Symposium on Low Power Electronics and Design, Seoul, Korea, pp. 134-139, August 2003.

  29. F. Li, D. Chen, L. He, and J. Cong, "Architecture Evaluation for Power-Efficient FPGAs," ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, pp. 175-184, February 2003.

  30. D. Chen, J. Cong, M. Ercegovac, and Z. Huang, "Performance-Driven Mapping for CPLD Architectures," ACM International Symposium on Field Programmable Gate Arrays, Monterey, California, pp. 39-47, February 2001.

  31. D. Chen, R. Colwell, H. Gelman, P. K. Chrysanthis, and D. Mosse, "A Framework for Experimenting with QoS for Multimedia Services," International Conference on Multimedia Computing and Networking, San Jose, California, January 1996.